OZ1KLK

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(last edit: 24. september 2012)

Entity

An Entity is the interface of a design
The entity contains a declaration part and a statement part. The declaration part declares the interface of the design, the statement part may contain passive statements, i.e. statements not assigning signals. The purpose of the statement part is to be able to verify the behavior of the signals declared in the declaration part, i.e. the ports.
Each entity in a design must have a unique name while each entity can have several architectures. Everything declared in an entity is automatically accessible in its architectures.
Note the order of the declarations in the declaration part of the entity.

Syntax

  entity EntityName is
    [Generic;]  
    [Port;]
    Declarations...
  [begin
    ConcurrentStatements...]                    {passive processes}
  end [entity] [EntityName];

Placement

 PACKAGE Pack IS
   ...
 END PACKAGE Pack;

 PACKAGE BODY Pack IS
   ...
 END PACKAGE BODY Pack;

 Blk:BLOCK 
   ...
 BEGIN 
   ...
 END BLOCK Blk;

 ENTITY Ent IS
   ...
 BEGIN 
   ...
 END ENTITY Ent;

 ARCHITECTURE Arc OF Ent IS
   ...
 BEGIN 
   ...
 END ARCHITECTURE Arc;

 CONFIGURATION Conf OF Ent IS
   ... 
 END CONFIGURATION Conf;

 Proc:PROCESS(...) 
   ...
 BEGIN 
   ...
 END PROCESS Proc;

 PROCEDURE P(...) IS
   ...
 BEGIN 
   ...
 END PROCEDURE P;

 FUNCTION F(...) RETURN Tp IS
   ...
 BEGIN
   ...
 END FUNCTION F;

Rules

Concurrent statements within the entity must be equivalent to passive processes, i.e. contain no signal assignments.

Synthesis

Each entity is synthesized as a separate hierarchical block, allowing you to control the hierarchy of the synthesized netlist, although some synthesis tools flatten the hierarchy by default.

Tips

If you need two versions of an entity with different ports, you must make two different entities. Entities cannot be overloaded. It is not necessary to write declarations and statements inside an entity. It is usually clearer and simpler to put them in the architecture.

Example

  library IEEE;
    use IEEE.Std_logic_1164.all;
    use IEEE.Numeric_std.all;

  entity Counter is
    generic (N: INTEGER);
    port (Clock, Reset, Enable: in Std_logic;
          Q: buffer Std_logic_vector (N-1 downto 0));
  end Counter;